Time-Domain Mixed-Signal MAC Processor

Deep neural networks (DNN) provide superior classification accuracy in a variety of machine learning applications, such as image/speech/sensor data processing. However, DNN requires intensive computing and memory resources due to the large amount of Multiply-and-Accumulate (MAC) operations, which brings challenges to energy-efficiently employ DNN algorithms in the general-purpose microprocessors under resource-constrained circumstances. Recently, a new technology to achieve energy-efficient MAC operation is proposed: time-domain computing. Multi-bit digital bitstream encoded as PWM signals and frequency varying signals to accomplish MAC operations. In this project, we choose this time-domain architecture to energy-efficiently do the MAC operation. We also use on-chip SRAM array as input data cache to save energy. The project mainly contains two parts. The first part is a Time-Domain Mixed-signal (TDMS) MAC processor that energy-efficiently implement 4-bit multiplication and addition. The second part is the data cache, which is an 8x8 8T SRAM array. In order to save energy consumption, voltages are scalable in different modules. Simulation result shows the TDMS MAC processor can achieve 4-bit multiplication-accumulation under the average power consumption of 65.71uW. The average energy efficiency is 0.3TOPS/W.